The present invention relates to a nonresilient test probe which is designed to uniformly contact pads of semiconductor devices, and more particularly pertains to a nonresilient or rigid test probe arrangement which is designed for investigating the integrity of silicon semiconductor device wafers or chips.
An extremely important facet of the semiconductor industry resides in being able to provide satisfactorily functioning semiconductor devices. In particular, such semiconductor devices may comprise wafers which are divided into areas which form chips, the shapes and dimensions of which are identical or as close to each other as is possible to obtain, so as to impart consistently uniform electrical properties thereto.
Generally, semiconductor devices on chips are ordinarily connected to each other with thin strips of metal, referred to in the art as interconnection metallurgy, which in turn contact the wafer surface through a series of pads or bumps, each 60-100 micrometers in size and situated peripherally at a pitch of 100 micrometers or less. Other connector pad configurations may include an array of electrical contacts or bumps which are distributed over an area; for instance, the widely employed C4 bumps (controlled collapse chip connects), which are usually each about 100-125 micrometers in diameter and arrayed at a pitch of about 200-250 micrometers. Such bumps or electrical contacts extend above the integrated circuits, are generally spherical or round in cross-sectional configuration, and are constituted of lead and tin (Pbxe2x80x94Sn).
Although silicon device wafers, which are divided into chips by being diced, are as closely uniform as possible to be produced through current manufacturing techniques, it is not always feasible that every chip can be produced so as to be perfect in nature, in view of unavoidable defects which are encountered during manufacture. In order to identify and to clearly distinguish between good and defective chips, electrical tests are performed prior to dicing of the wafers into chip areas, to thereby facilitate the sorting out of good chips and eliminating defective chips prior to the next step of manufacture.
Ordinarily, active testing of the wafers is performed by a test facility in which the pads or areas on wafers possessing arrays of bumps, such as of C4 bumps, are contacted by an assembly incorporating test probes. In order to successfully probe the integrity of the pads or bumps, it is desirable that an oxide layer, which inevitably forms on the surface of the C4 bumps, be ruptured end penetrated to ensure a good electrical contact with the probe while employing only a minimal force to inhibit damaging the pads or bumps. The plane of the test probe should be constructed to be as flat as possible so as to facilitate the simultaneous contacting of all pads or bumps by the test probe.
In recent times, so-called cobra probes have been utilized in conjunction with the probing or testing of the integrity of semiconductor device wafers possessing an area with an array of C4 bumps or similar electrical contacts. A cobra probe normally comprises a plurality of wires which are mounted in parallel with their respective ends terminating in two planes which extend transversely of the axes of the probe wires. The wires are preshaped and flexible, which fulfills two of the numerous requirements to render them highly successful in probing silicon device wafers. However, the rapid advance in semiconductor technology, in which the number of pads for I/O (Input/Output) or power/ground has increased and the devices are required to be tested at high switching speeds, has limited the use of cobra probe technology. Furthermore, the cobra wires have a tendency at times to short out to closely situated adjacent wires or to carry dirt and fragments which are dropped on the array of bumps or chips being tested and which can cause short or open circuits therein.
Moreover, peripheral probing of CMOS semiconductor devices with the use of cantilever probes has been extremely successful in the semiconductor industry. Nevertheless, increased semiconductor device contact or bump densities leading to closer pitch and reduced pad size requirements, have resulted in a requirement for more precise alignment and closer planarity in peripheral probing. This type of probing also faces technological challenges and limitations in its applicability.
Membrane probe technology is also being more widely employed in order to replace previous needle-type or wire probes for the purpose of resting wafers having semiconductor device pads which are in more closely spaced relationships. Although membrane probes have been improved in recent years, they have not yet reached their full potential for peripheral probing of semiconductor device wafers. A lack of good electrical contact, or the inability of the probes to break through the oxide layer which forms on the pads, have been primary causes in the failure of membrane probes to provide satisfactory testing results.
For example, cobra probes which are considered to be satisfactory for testing of semiconductor wafers or chips with C4 bumps, have been employed in this technology and are disclosed in Byrnes et al., U.S. Pat. No. 4,027,935, which is assigned to the common assignee of the present application.
Membrane or pellicle probes which have been found to be generally satisfactory in this technology for the testing of electrical contacts or C4 bumps for semiconductor devices can be ascertained from the disclosure of Byrnes et al., U.S. Pat. No. 5,207,585, which is assigned to the common assignee of the present application. Byrnes et al. utilizes an interface pellicle probe for testing semiconductor devices which comprise copper bumps on a copper-plated polyimide membrane of a material such as Kapton (registered trademark of Dupont Corp.). The distinction between the approach taken by Byrnes et al. and those previously employed for the peripheral pads is that in Byrnes et al. the top and bottom. surfaces of the probes arrayed over areas are shaped; in effect, the upper bump side providing contact with the space transformer and the lower side facing towards the semiconductor are configured so as to permit an easy penetration into the C4 bumps.
In addition to the above-mentioned Byrnes et al. U.S. patents, other publications which are concerned with diverse types of systems for the testing of the functional integrity of electrical contacts for semiconductor wafers or the like, are disclosed in Sano. U.S. Pat. No. 5,604,446; Atkins et al., U.S. Pat. No. 5.570,032; Sano, U.S. Pat. No. 5,559,446; Sano, U.S. Pat. No. 5,550,482; Abe et al., U.S. Pat. No. 5,521,522; Tarzwell et al., U.S. Pat. No. 5,066,907; Leslie and Matta, in xe2x80x9cMembrane Probe Card Technology (The Future For High Performance Wafer Test)xe2x80x9d in IEEE International Test Conferences; Higashi et al., U.S. Pat. No. 5,438,223; Yamamoto et al., U.S. Pat. No. 5,575,662 and Fujita, U.S. Pat. No. 5,576,630. However, many of these suffer through contact fails and none of these pertains to wafer test probes analogous to those of the present invention to be used with area array probing of C4 contacts.
In summation, heretofore for area arrays with C4 bump semiconductor device pads, cobra probes have been found to be generally satisfactory. However, more recently on the basis of ever increasing industry demands and advances in the technology, cobra probes have been challenged in their ranges of applicability. The semiconductor device densities of the chips have increased extensively along with the need for providing more device pads as test points, in effect, at a close pad pitch and size (4 on 8 mil or lower).
Moreover, the increased density or packing of more semiconductor devices on a chip requires the presence of larger chips (10-20 mm or more), and additionally requires larger bandwidths (greater than 200 MZ). A modern cobra probe assembly must contact more than 1500-2000 pads in an average chip of 15 mm size. Thus, upper and lower dies of such probe equipment become quite large and are prone to warping or arching, which frequently leads to a failure of the probing process. Furthermore, cobra probes employed in an extremely dense packing situation, particularly with large chips, are frequently prone to electrical shorts. Moreover, the normally considerable length of a cobra probe renders it unsuitable for large bandwidths. In contrast, the relatively short probes of peripherally bumped membranes could present a solution to the problem, but cannot be fully implemented because of failures related to contact resistance or non-optimized contact pressure in the implementing systems.
The present invention provides a nonresilient probe wafer interface arrangement which can be utilized with high density chips and with larger bandwidths. The arrangement also enhances wafer test capabilities beyond those attainable with conventional cobra probes.
Another object of the present invention is to determine test system parameters, such as the planarity present between a probe and a test fixture, which is required for successful wafer testing when utilizing rigid probes.
Another object of the subject invention is to eliminate pliant conditions encountered by current test fixtures, probes and the C4 bumps or pads, (run-off) which are adverse to the attainment of satisfactory results with rigid probes. Any condition of pliancy between the wafer being tested and the probe fixture assembly should be so negligible as to be practically nonexistent, to ensure practically perfect parallelism between the wafer and the test fixture.
A further object of the present invention is the provision of a test fixture and rigid probe assembly which is capable of improved testing or probing of silicon wafers, and wherein a vacuum fixture is adapted to tightly maintain the membrane probe against the conductive pads of a space transformer so as to provide good electrical contact with the semiconductor device pads during wafer testing.
A still further object is to maintain electrical contact by employing a vacuum fixture which is designed to enhance and not to adversely impact upon the efficiency of usage and throughput of the test equipment. Moreover, the tests can be readily conducted at elevated temperatures of up to about 85xc2x0 C. without degrading the quality of tests which are normally attained at room or ambient temperature
Yet another object of the invention is to provide for minimum deformation of the C4 bumps or pads during testing thereof by applying as low a force as possible during the testing procedure, thus enabling chips to be used as-tested or reflowed for the next step of manufacture.